1. Field of the Invention
The present invention relates to a driving method for driving a display panel such as an AC driven plasma display panel or an electroluminescence display panel.
2. Description of the Related Art
Currently, display panels comparing capacitive light emitting elements such as a plasma display panel (hereinafter referred to as the “PDP”), an electroluminescence display panel (hereinafter referred to as the “ELP”) and the like have been brought into practical use to provide wall-mounted television sets.
FIG. 1 generally shows such a plasma display panel which has a PDP as a display panel (see, for example, Japanese Patent Kokai No. 2002-156941).
In FIG. 1, a PDP 10 as a plasma display panel comprises row electrodes Y1-Yn and X1-Xn which form pairs of row electrodes X, Y, each of which corresponds to each line (first to n-th rows) of one screen. The PDP 10 is further formed of column electrodes Z1-Zm corresponding to respective columns (first to m-th columns) of one screen, which are orthogonal to the row electrode pairs and across a dielectric layer and a discharge space, not shown. A discharge cell serving as a pixel is formed at the intersection of a pair of row electrodes (X, Y) with a column electrode Z.
Here, since each discharge cell emits light by discharging, it has only two states: a light emitting state at the highest luminance and an unlit state. In other words, the discharge cell can represent only two levels of luminance, i.e., the lowest luminance and highest luminance if no measures are taken therefor.
Thus, a driving apparatus 100 conducts a gradation driving scheme which employs a sub-field method for providing halftone luminance levels corresponding to an input video signal for the PDP 10 which is comprised of such a light emitting element as each pixel cell.
The sub-field method involves converting an input video signal into N-bit pixel data corresponding to each pixel, and dividing one field display period into N sub-fields corresponding to respective bit digits of the N bits. Each of the sub-fields is assigned the number of times of discharge generated corresponding to a weighting coefficient applied to the sub-field, so that this discharge is selectively generated only in sub-fields in accordance with the video signal. In this event, a halftone luminance corresponding to the video signal can be accomplished by a total number of times the discharge is generated in each sub-field (within one field display period).
A selective erasure addressing method is known as a method of driving a PDP to provide halftone luminance by use of the sub-field method.
FIG. 2 is a timing chart showing applying timings at which the driving apparatus 100 applies a variety of driving pulses to the column electrodes and the row electrode pairs of the PDP 10 in one sub-field based on the selective erasure addressing method (see, for example, FIG. 2 in Japanese Patent Kokai No. 2002-156941).
The driving apparatus 100 first applies a reset pulse RPX of negative polarity to the row electrodes X1-Xn, and a reset pulse RPY of positive polarity to the row electrodes Y1-Yn (simultaneous reset stage Rc). In response to the application of these reset pulses RPX and RPY, all the discharge cells in the PDP 10 are reset or discharged to uniformly form a predetermined amount of wall charge in each of the discharge cells. In this way, all the discharge cells are initially set once into a light emission mode.
Next, the driving apparatus 100 converts the input video signal, for example, into 8-bit pixel data for each pixel. The driving apparatus 100 divides the pixel data for each bit digit to generate pixel data bits, and generates a pixel data pulse having a pulse voltage in accordance with the logical level of each of the pixel data bits. For example, the driving apparatus 100 generates the pixel data pulse DP at a high voltage when the pixel data bit is at logical level “1” and at a low voltage (zero volt) when the pixel data bit is at logical level “0.” Then, the driving apparatus 100 sequentially applies the column electrodes Z1-Zm with the pixel data pulses DP for one line (m pulses). Further, the driving apparatus 100 sequentially applies the row electrodes Y1-Yn with a scanning pulse SP as shown in FIG. 2 in synchronism with the timings of applying the pixel data pulses DP (pixel data writing stage Wc). In this event, a discharge occurs only in discharge cells at intersections of those row electrodes which have been applied with the scanning pulse SP and those column electrodes which have been applied with the pixel data pulses at high voltage (selective writing discharge) to erase wall charges remaining in these discharge cells. In this way, those discharge cells, which have been initialized to the light emission mode in the simultaneous reset stage Rc, proceed to a light extinction mode. On the other hand, those discharge cells which have been applied with the scanning pulse SP but also applied with low voltage image data pulses do not undergo the selective writing discharge, and remain in the initialized state in the simultaneous reset stage Rc, i.e., the light emission mode.
Next, as shown in FIG. 2, the driving apparatus 100 repeatedly applies a sustain pulse IPX of positive polarity to the row electrodes X1-Xn and repeatedly applies a sustain pulse IPY of positive polarity to the row electrodes Y1-Yn (light emission sustaining stage Ic). In this event, those discharge cells in which the wall charge remains, i.e., only discharge cells in the light emission mode discharge each time they are alternately applied with the sustain pulses IPX, IPY (sustain discharge). In other words, only discharge cells which have been set into the light emission mode in the pixel data writing stage Wc repeat the light emission associated with the sustain discharge a number of times corresponding to the weight coefficient applied to each sub-field to sustain their light emitting state. It should be noted that the number of times the sustain pulses IPX, IPY are applied in one sub-field has been previously set in accordance with the weighting coefficient applied to each sub-field.
Next, the driving apparatus 100 applies the row electrodes X1-Xn with an erasure pulse EP as shown in FIG. 2 (erasure stage E). In this way, all the discharge cells are simultaneously erased or discharged to extinguish the wall charges remaining in the respective discharge cells.
However, when the foregoing driving is applied to a capacitive display panel such as the PDP or ELP, the application of the pixel data pulse DP, for example, results in charging and discharging of not only display lines for which a data write is intended, but also display lines for which the data write is not intended, and the capacitance must further be charged and discharged between adjacent column electrodes.
Consequently, a problem arises in that large power consumption is accompanied with a pixel data write.
It is an object of the present invention to provide a display panel driving method which is capable of reducing the power consumption.